1. Field of the Invention
The present invention relates to semiconductor devices in general and, more particularly, to the configuration of Leads-Over-Chip (LOC) semiconductor devices.
2. State of the Art
Modern packaged integrated circuits (IC) comprise one or more encapsulated semiconductor devices, dies or chips within a protective "package" of plastic, ceramic or other moldable material. Typically, a large number of dice are formed from a wafer made from a semiconductor material such as silicon, germanium or gallium arsenide. Microscopic circuits are formed on a surface of each semiconductor die by photolithographic techniques and typically attached to a lead frame with conductive wires. More particularly, a plurality of leads of the lead frame is connected to bond pads on the semiconductor die or dice, enabling the dice to be electrically interconnected to an external electrical host apparatus, typically mounted on a circuit board.
Early semiconductor devices used relatively large semiconductor dice with peripheral bond pads. Off-die leads were wire-bonded to the peripheral bond pads. With the later introduction of Leads-Over-Chip (LOC) technology, the package size using large semiconductor die could be reduced. This was accomplished by using centrally positioned conductive bond pads on the semiconductor dice and insulatively bonding the inner leads to the semiconductor die surface close to the bond pads for wire connection. Thus, the semiconductor die and lead frame were more intimately joined, and the outer leads could be formed close to or adjacent the semiconductor dice.
In early LOC devices, the semiconductor die were relatively large, consuming most of the package space. The numbers of leads attached to the semiconductor die were also limited. Thus, wide and short leads which closely approached the bond pads on the active surface of the semiconductor die were used. The resulting wirebonds were short, and the inductance between the semiconductor die and the host apparatus was low. Examples of such are found in U.S. Pat. No. 5,227,661 of Heinen, U.S. Pat. No. 5,233,220 of Lamson et al., U.S. Pat. No. 5,252,853 of Michii, U.S. Pat. No. 5,331,200 of Teo et al., U.S. Pat. No. 5,418,189 of Heinen, and U.S. Pat. No. 5,466,888 of Beng et al.
In later generation IC devices, the semiconductor dice have become progressively smaller while the numbers of leads of the lead frame have typically increased. As a result, the inner leads of the lead frame of such devices must of necessity be reduced in lead width and pitch, both of which increase the lead inductance and slow the speed of the device. In addition, a minimum lead width is required for high-quality wire bonding. The high density of wire connections typically makes wire bonding more difficult and increases the frequency of bond failures. Furthermore, with very small semiconductor dice, the very fine wires may be very long, resulting in "wire sweep", sagging, short circuiting and bond failure during encapsulation of the semiconductor die and lead frame. For a very small semiconductor die, fitting all of the inner leads of the lead frame onto the active surface of the semiconductor die is generally not possible, given the present size and space limitations. Even conventional off-die wire bonding is very difficult or not possible in production scale.
High inductance and reduced speed limit the usefulness of packaged semiconductor dice with long, narrow leads, and shorting or destruction of the wire bonds will make the device useless.
The required spacing, width and length of leads and wires have become serious limitation in further miniaturization of semiconductor dies and their packages. While complex integrated circuits may be formed in very small semiconductor die, connecting such a die or dice to leads for interconnection to a host apparatus while maintaining the semiconductor die characterization is very difficult.
There have been various attempts at overcoming the high inductance or interactive conductance effects of small semiconductor die devices. For example, in U.S. Pat. No. 5,521,426 of Russell is disclosed a lead-on-chip (LOC) device with long, narrow leads. In order to decrease the capacitance between the leads and the die and increase lead strength, the leads are stamped or rolled to have a non-rectangular cross-section such as a "U" configuration. Thus, the strength of the lead and its cross-sectional area are increased, resulting in less lead sag and lowered capacitative interaction. However, the cost of producing such leads is considerable, and the package thickness is increased. Furthermore, the method does not increase the size of wire bonding areas on the lead fingers, and the wire bonding operation is no easier.
In U.S. Pat. No. 4,984,059 of Kubota et al., a semiconductor device is shown with the long sides of the die parallel to the rows of outer lead ends, i.e. in a non-transverse configuration. The device has a very limited number of pins.
U.S. Pat. No. 5,218,229 of Farnworth discloses a lead frame design in which a semiconductor die with opposing rows of peripheral bond pads on the active surface of the die is positioned for off-die wire attachment. The rows of bond pads are perpendicular to the two rows of outer lead ends.
U.S. Pat. No. 4,989,068 of Yasuhara et al. shows a semiconductor device in which all leads are LOC leads between two rows of peripheral bond pads.
None of the above prior art documents discloses a high-speed semiconductor device having a large number of bond pads on a small die, whereby the lead inductance is minimized and wire bonding operations are enhanced. The need exists for such a device.